Conventionally, layouts of semiconductor integrated circuits (ICs) are designed by arranging circuit elements called standard cells. A standard cell has a functional block, such as an AND gate, an OR gate, or a flip-flop, and an internal wiring pattern designed in advance. In large scale integration (LSI) design, standard cells registered in a library are generally aligned in rows and are wired using channels between the rows to realize a desired LSI.
Standard cells include active areas on which many gates are formed. Typically, the last gate formed on the active area (the gate formed nearest the end of the active area formed on the standard cell) exhibits problems. Specifically, the transistor represented by the last gate has performance problems including contact problems, yield problems, and variability problems. These problems arise from the inability to achieve a well-controlled, desirable structure at the end of the active area. For example, under current processing, gates formed at ends of active areas are troubled by undesirable epitaxial growth, facets, undercutting caused by wet etches, and undesirable material left in the topography.
In order to avoid the problems faced by the last gate on an active area, attempts have been made to arrange circuits to avoid having a last gate. However, there is necessarily a last gate somewhere in the design. Other attempts have formed a dummy gate at the end of the active area, with a full active overlap. However, such a design uses a significant amount of area. Another strategy has been to add half of a dummy gate along with an active area tuck under the dummy gate. Again, this method uses a significant amount of area.
In order to avoid the problems associated with the last gate, it is envisioned herein that the active area not be bounded by a standard cell. Rather, each standard cell can be provided with an active area that extends from cell boundary to cell boundary. When arranged, adjacent cells have aligned active areas and form a continuous active area. As a result, last gates are minimized or eliminated.
In order to utilize a continuous active area, gates on each side of the interface between standard cells must be isolated. Specifically, NMOS gates must be tied to ground and the PMOS gates must be tied to the power rail. Yet conventional tying methods, such as vias, result in use of a significant amount of IC area, leading to the design problems associated with the dummy gate methods noted above.
Accordingly, it is desirable to provide integrated circuits and methods for fabricating integrated circuits having continuous active areas. In addition, it is desirable to provide integrated circuits and methods for fabricating integrated circuits which provide for electrical connection between gate strips and interconnects without taking up additional IC space. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.